When designing an integrated circuit including semiconductor devices, engineers or designers typically rely on computer design tools to help create an integrated circuit schematic or design, which can include a multitude of individual devices, such as transistors, coupled together to perform a certain function. To actually fabricate the integrated circuit device in or on a semiconductor substrate, the integrated circuit device schematic must be translated into a physical representation or layout, which itself can be transferred onto the surface of the semiconductor substrate. Computer-aided design (CAD) tools can be used to assist layout designers with translating the discrete circuit elements into shapes, which will embody the devices themselves in the completed integrated circuit device. These shapes make up the individual components of the circuit, such as gate electrodes, diffusion regions, metal interconnects and the like.
Vertical conductive paths or vias are typically formed in integrated circuits to provide electrical interconnection to devices and/or horizontal conductive lines or layers during back-end-of-line processing. While via shapes are provided by computer design processes, via formation during integrated circuit fabrication may fail to provide the via at the correct location and/or with the correct via shape. For example, via/line mis-alignment or “overlay error” may occur during lithographic patterning. By “mis-alignment” it is meant the deviation from the perfect alignment (or overlay) of the subsequent line (or via) level to the via (or line) level thereunder that is intended to directly connect the line (via) level to the via (line) level directly below. Mis-alignment may be due to the limitation of the lithography tool employed or processing errors. The mis-aligned via/line causes degradation in performance, such as increasing the contact resistance of the metal line to the via, and deterioration in reliability of the resultant metal interconnects, due to enhancement of failure mechanisms such as electromigration.
Accordingly, it is desirable to provide an improved method for retargeting a via to compensate for processing limitation or errors during integrated circuit fabrication. In addition, it is desirable to provide a method for fabricating an integrated circuit using such retargeted vias. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.